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FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver product specification supersedes data of 1998 sep 04 2000 apr 18 integrated circuits
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2 2000 apr 18 853-2118 23499 features ? latched, registered or straight through in either a to b or b to a path ? drives heavily loaded backplanes with equivalent load impedances down to 10 w . ? high drive 100ma btl open collector drivers on b-port ? allows incident wave switching in heavily loaded backplane buses ? reduced btl voltage swing produces less noise and reduces power consumption ? built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity ? compatible with ieee futurebus+ or proprietary btl backplanes ? each btl driver has a dedicated bus gnd for a signal return ? controlled output ramp and multiple gnd pins minimize ground bounce ? glitch-free power up/power down operation ? low i cc current ? tight output skew ? supports live insertion ? pins for the optional jtag boundary scan function are provided ? high density packaging in plastic quad flatpack ? 5v compatible i/o on a-port description the FBL2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the a-to-b or b-to-a direction. the FBL2031 is intended to provide the electrical interface to a high performance wired-or bus. quick reference data symbol parameter typical unit t plh t phl propagation delay an to bn 2.7 ns t plh t phl propagation delay bn to an 4.4 4.2 ns c o output capacitance (b0 bn only) 6 pf i ol output current (b0 bn only) 100 ma ain to bn (outputs low or high) 11 i cc supply current bn to aon (outputs low) 22 ma bn to aon (outputs high) 18 ordering information package v cc = 3.3v 10%; t amb = 40 c to +85 c dwg no. 52-pin plastic quad flat pack (pqfp) FBL2031bb sot379-1
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 3 pin configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 bus gnd b1 bus gnd b2 bus gnd b3 bus gnd b4 bus gnd b5 bus gnd b6 bus gnd logic gnd a2 a3 a4 logic gnd a5 a6 a7 logic gnd bg gnd b7 bg v cc a1 a0 oea bias v b0 v cc v cc 9-bit latched/registered transceiver FBL2031 52-lead pqfp logic gnd bus gnd sel0 oeb0 b8 a8 oeb1 tck (option) tms (option) bus gnd v cc tdo (option) tdi (option) sel1 lcba lcab logic gnd logic gnd logic gnd logic gnd sg00087 pin description symbol pin number type name and function a0 a8 50, 52, 2, 4, 6, 8, 10, 12, 14 i/o bicmos data inputs/3-state outputs (ttl) b0 b8 40, 38, 36, 34, 32, 30, 28, 26, 24 i/o data inputs/open collector outputs, high current drive (btl) oeb0 46 input enables the b outputs when high oeb1 45 input enables the b outputs when low oea 47 input enables the a outputs when high bus gnd 25, 27, 29, 31, 33, 35, 37, 39, 41 gnd bus ground (0v) logic gnd 51, 1, 3, 5, 7, 9, 11, 13 gnd logic ground (0v) v cc 23, 43, 49 power positive supply voltage bias v 48 power live insertion pre-bias pin bg v cc 17 power band gap threshold voltage reference bg gnd 19 gnd band gap threshold voltage reference ground sel0 20 input mode select sel1 15 input mode select lcab 18 input a to b clock/latch enable (transparent latch when low) lcba 16 input b to a clock/latch enable (transparent latch when low) tms 42 input test mode select (optional, if not implemented then no connect) tck 44 input test clock (optional, if not implemented then no connect) tdi 22 input test data in (optional, if not implemented then no connect) tdo 21 output test data out (optional, if not implemented then shorted to tdi)
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 4 description the ttl-level side (a port) has a common i/o. the common i/o, open collector b port operates at btl signal levels. the logic element for data flow in each direction is controlled by two mode select inputs (sel0 and sel1). a a00o configures latches in both directions. a a10o configures thru mode in both directions. a a01o configures register mode in both directions. a a11o configures register mode in the a-to-b direction and latch mode in the b-to-a direction. when configured in the buffer mode, the inverse of the input data appears at the output port. in the register mode, data is stored on the rising edge of the appropriate clock input (lcab or lcba). in the latch mode, clock pins serve as transparent-low latch enables. regardless of the mode, data is inverted from input to output. the 3-state a port is enabled by asserting a high level on oea. the b port has two output enables, oeb0 and oeb1 . only when oeb0 is high and oeb1 is low is the output enabled. when either oeb0 is low or oeb1 is high, the b port is inactive and is pulled to the level of the pull-up voltage. new data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-state (a port) or inactive (b port). the b-port drivers are low-capacitance open collectors with controlled ramp and are designed to sink 100ma. precision band gap references on the b-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55v. the b-port interfaces to abackplane transceiver logico (see the ieee 1194.1 btl standard). btl features low power consumption by reducing voltage swing (1v p-p, between 1v and 2v) and reduced capacitive loading by placing an internal series diode on the drivers. btl also provides incident wave switching, a necessity for high performance backplanes. output clamps are provided on the btl outputs to further reduce switching noise. the av oh o clamp reduces inductive ringing effects during a low-to-high transition. the av oh o clamp is always active. the other clamp, the atrapped reflectiono clamp, clamps out ringing below the btl 0.5v v ol level. this clamp remains active for approximately 100ns after a high-to-low transition. to support live insertion, oeb0 is held low during power on/off cycles to insure glitch- free b port drivers. proper bias for b port drivers during live insertion is provided by the bias v pin when at a 3.3v level while v cc is low. the bias v pin is a low current input which will reverse-bias the btl driver series schottky diode, and also bias the b port output pins to a voltage between 1.62v and 2.1v. this bias function is in accordance with ieee btl standard 1194.1. if live insertion is not a requirement, the bias v pin should be tied to a v cc pin. the logic gnd and bus gnd pins are isolated inside the package to minimize noise coupling between the btl and ttl sides. these pins should be tied to a common ground external to the package. each btl driver has an associated bus gnd pin that acts as a signal return path and these bus gnd pins are internally isolated from each other. in the event of a ground return fault, a ahardo signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. as with any high power device, thermal considerations are critical. it is recommended that airflow (300ifpm) and/or thermal mounting be used to ensure proper junction temperature. package thermal characteristics parameter condition 52-pin plastic qfp q ja still air 80 c/w q ja 300 linear feet per minute air flow 58 c/w q jc thermally mounted on one side to heat sink 20 c/w
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 5 function table mode inputs outputs mode an bn * oeb0 oeb1 oea lcab lcba sel0 sel1 an bn an to bn thru mode l e h l l x x h l input h** an to bn thr u mode h e h l l x x h l input l an to bn trans p arent latch l e h l l l x l l input h** an to bn transparent latch h e h l l l x l l input l an to bn latch and read l e h l l x l l input h** an to bn latch and read h e h l l x l l input l bn outputs latched and read (preconditioned latch) x e h l x h x l l x latched data an to bn register l e h l l x x h input h** an to bn register h e h l l x x h input l bn to an thru mode e l disable h x x h l h input bn to an thr u mode e h disable h x x h l l input e l disable h x l l l h input bn to an trans p arent latch e h disable h x l l l l input bn to an transparent latch e l disable h x l h h h input e h disable h x l h h l input e l disable h x l l h input bn to an latch and read e h disable h x l l l input bn to an latch and read e l disable h x h h h input e h disable h x h h l input an outputs latched and read e x x x h x h l l latched data x (preconditioned latch) e x x x h x h h h latched data x bn to an register e l disable h x l h h input bn to an register e h disable h x l h l input disable bn out p uts x x l x x x x x x x h** disable bn o u tp u ts x x x h x x x x x x h** disable an outputs x x x x l x x x x z x function select table mode selected sel0 sel1 thru mode h l register mode (an to bn) x h latch mode (an to bn) l l register mode (bn to an) l h latch mode (bn to an) l l latch mode (bn to an) h h notes: h = high voltage level l = low voltage level l = low voltage level one set-up time prior to the low-to-high lcxx transition h = high voltage level one set-up time prior to the low-to-high lcxx transition x = don't care z = high-impedance (off) state e = input not externally driven = low-to-high transition h** = goes to level of pull-up voltage bn * = precaution should be taken to ensure b inputs do not float. if they do, they are equal to low state. disable = oeb0 is low or oeb1 is high.
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 6 logic diagram decode out in 46 45 oeb0 oeb1 47 oea 14 a8 dq clk 24 b8 38 18 lcab 20 sel0 28 30 32 34 36 btl tms tck tdi tdo 42 44 22 21 (jtag boundary scan pins) logic gnd = 1, 3, 5, 7, 9, 11, 13, 51 bus gnd = 25, 27, 29, 31, 33, 35, 37, 39, 41 bias v = 48 v cc = 23, 43, 49 bg v cc =17 bg gnd = 19 dq e mux a ? b qd mux a ? b 26 b7 12 a7 mux a ? b 52 10 8 6 4 2 ttl a1 mux a ? b mux a ? b b1 40 50 mux a ? b mux a ? b b0 dq clk dq e dq clk dq e d q clk d q e d q clk d q e d q e dq e dq clk d q clk d q e 15 sel1 16 lcba d q clk mux a ? b a0 sg00061
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 7 absolute maximum ratings operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted these lim its are over the operating free-air temperature range. symbol parameter rating unit v cc supply voltage 0.5 to +4.6 v v in p ut voltage ai0 ai6, oeb0, oebn , oean 0.5 to +7.0 v v in inp u t v oltage b0 b8 0.5 to +3.5 i in input current v in 0 50 v out voltage applied to output in high output state 0.5 to +7.0 v i o current applied to output in ao0 ao8 64, 64 ma i out low output state/high output state b0 b8 200 t stg storage temperature 65 to +150 c recommended operating conditions symbol parameter commercial limits v cc = 3.3v 10%; t amb = 40 to +85 c unit min typ max v cc supply voltage 3.0 3.3 3.6 v v high level in p ut voltage except b0 b8 2.0 v v ih high - le v el inp u t v oltage b0 b8 1.62 1.55 v low level in p ut voltage except b0 b8 0.8 v v il lo w- le v el inp u t v oltage b0 b8 1.47 i ik input clamp current 18 ma i oh high-level output current ao0 ao8 32 ma i o low level out p ut current ao0 ao8 +32 ma i ol lo w- le v el o u tp u t c u rrent b0 b8 100 c ob output capacitance on b port 6 7 pf t amb operating free-air temperature range 0 +70 c live insertion specifications symbol parameter limits unit symbol parameter min typ max unit v biasv bias pin voltage voltage difference between the bias voltage and v cc after the pcb is plugged in. 0.5 v i s bias pin (i bia s v ) input v cc = 0 v, bias v = 3.6v 1.2 ma i biasv ( biasv ) dc current v cc = 3.3v, bias v = 3.6v 10 m a v bn bus voltage during prebias b0 b8 = 0v, bias v = 3.3v 1.62 2.1 v i lm fall current during prebias b0 b8 = 2v, bias v = 1.3 to 2.5v 1 m a i hm rise current during prebias b0 b8 = 1v, bias v = 3 to 3.6v 1 m a i bn peak peak bus current during insertion v cc = 0 to 3.3v, b0 b8 = 0 to 2.0v, bias v = 2.7 to 3.6v, oeb0 = 0.8v, t r = 2ns 10 ma i o off power u p current v cc = 0 to 3.3v, oeb0 = 0.8v 100 m a i ol off po w er u p c u rrent v cc = 0 to 1.2v, oeb0 = 0 to 5v 100 m a t gr input glitch rejection v cc = 3.3v 1.0 1.35 ns
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 8 dc electrical characteristics over recommended operating free-air temperature range unless otherwise noted. symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min typ 2 max unit i oh high level output current b0 b8 v cc = max, v il = max, v oh = 1.9v 100 m a i o power off out p ut current b0 b8 v cc = 0v, v il = max, v oh = 1.9v 100 m a i off po w er - off o u tp u t c u rrent b0 b8 v cc = 0v, v il = max, v oh = 1.9v @ 85 c 300 m a hi h l l t t 3 v cc = min to max v cc 0.2 v v oh high-level output voltage ao0 ao8 3 v cc = min; i oh = -8ma 2.4 v voltage v cc = min; i oh = -32ma 2.0 v ao0 ao8 3 v cc = min; i ol = 16ma 0.4 v v o low level out p ut voltage ao0 ao8 3 v cc = min; i ol = 32ma 0.5 v v ol lo w- le v el o u tp u t v oltage b0 b8 v cc = min, i ol = 4ma 0.5 v v cc = min, i ol = 100ma 0.75 1.0 1.20 v v ik input clamp voltage v cc = min, i i = i ik = 18ma 0.85 1.2 v control pins v cc = 3.6v; v i = v cc or gnd 1.0 i i input leakage current control/ ai0 ai8 v cc = 0v or 3.6v; v i = 5.5v 10 m a i g ai0 ai8 v cc = 3.6v; v i = v cc 1 m note 4 v cc = 3.6v; v i = 0v 5 v cc = max, v i = 1.9v 100 m a i ih high-level input current b0 b8 v cc = max, v i = 3.5v, note 5 100 ma v cc = max, v i = 3.75v @ 40 c 100 ma i il low-level input current b0 b8 v cc = max, v i = 0.75v 100 m a i ozh off-state output current ao0 ao8 v cc = max, v o =3v 5 m a i ozl off-state output current ao0 ao8 v cc = max, v o = 0.5v 5 m a i cch b to a v cc = max, outputs high 18 32 ma i ccl b to a v cc = max, outputs low 22 37 ma i cc supply current (total) i cch a to b v cc = max, outputs high 11 16 ma i ccl a to b v cc = max, outputs low 11 16 ma i ccz v cc = max 18 32 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operation conditions for the applic able type. 2. all typical values are at v cc = 3.3v, t a = 25 c. 3. due to test equipment limitations, actual test conditions are v ih = 1.8v and v il = 1.3v for the b side. 4. unused pins are at v cc or gnd. 5. for b port input voltage between 3 and 5 volt; i ih will be greater than 100ma but the part will continue to function normally (clamping circuit is active). this is not a tested condition.
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 9 ac electrical characteristics b to a specifications symbol parameter test condition t amb = +25 c, v cc = 3.3v, t amb = 40 to +85 c, v cc = 3.3v 10%, unit min typ max min max f max maximum clock frequency waveform 4 120 150 mhz t plh t phl propagation delay (thru mode) bn to an waveform 1, 2 2.8 3.0 4.3 4.5 5.9 6.0 2.2 2.6 6.8 7.3 ns t plh t phl propagation delay (transparent latch) bn to an waveform 1, 2 2.8 3.4 4.9 5.0 7.0 6.6 1.8 2.8 8.4 7.8 ns t plh t phl propagation delay lcba to an (latch) waveform 1, 2 7.7 7.5 10.2 10.1 13.0 12.9 6.1 6.1 15.6 15.4 ns t plh t phl propagation delay lcba to an (register) waveform 1, 2 2.7 3.0 4.2 4.5 5.7 6.1 2.1 2.4 6.7 6.9 ns t plh t phl propagation delay sel0 or sel1 to an (inverting) waveform 1, 2 2.9 1.9 5.8 5.8 9.1 10.4 2.2 1.2 10.5 11.6 ns t plh t phl propagation delay sel0 or sel1 to an (non-inverting) waveform 1, 2 2.0 2.8 5.9 5.6 10.3 8.8 1.4 2.2 12.3 10.0 ns t pzh t phz output enable time from high or low oea to an waveform 5, 6 3.0 4.0 4.4 5.6 5.7 7.3 2.6 3.2 6.6 8.3 ns t pzl t plz output disable time to high or low oea to an waveform 5, 6 2.6 1.4 4.0 2.6 5.4 3.7 2.1 1.0 6.0 4.4 ns t tlh t thl output transition time, an port 10% to 90%, 90% to 10% test circuit and waveforms 0.2 0.1 2.0 1.2 ns t sk (o) output to output skew for multiple channels 1 waveform 3 0.5 1.0 1.5 ns t sk (p) pulse skew 2 ? t phl t plh ? max waveform 2 0.5 1.0 1.5 ns notes: 1. ? t pn actual t pm actual ? for any data input to output path compared to any other data input to output path where n and m are either lh or hl. skew times are valid only under same test conditions (temperature, v cc , loading, etc.). t sk (0) compares t plh on a given path to t plh on any other path or compares t phl on a given path to t phl on any other path. 2. t sk (p) is used to quantify duty cycle characteristics. in essence it compares the input signal duty cycle to the corresponding out put signal duty cycle (50mhz input frequency and 50% duty cycle, tested on data paths only).
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 10 ac electrical characteristics a to b 9 w load specifications symbol parameter test condition t amb = +25 c, v cc = 3.3v, t amb = 40 to +85 c, v cc = 3.3v 10%, unit min typ max min max t plh t phl propagation delay (thru latch) an to bn waveform 1, 2 1.4 1.3 2.6 2.5 3.8 3.8 1.0 1.0 4.9 4.2 ns t plh t phl propagation delay (transparent latch) an to bn waveform 1, 2 1.7 2.0 2.9 3.5 4.2 5.0 1.0 1.5 5.4 5.7 ns t plh t phl propagation delay lcab to bn (latch) waveform 1, 2 8.8 8.4 11.6 11.0 14.5 13.7 6.7 6.7 17.9 16.6 ns t plh t phl propagation delay lcab to bn (register) waveform 1, 2 2.3 2.5 3.6 4.0 5.0 5.4 1.4 1.9 6.2 6.4 ns t plh t phl propagation delay sel0 or sel1 to bn (inverting) waveform 1, 2 2.3 1.3 3.8 4.8 5.5 8.8 1.2 1.0 7.0 9.6 ns t plh t phl propagation delay sel0 or sel1 to bn (non-inverting) waveform 1, 2 2.0 2.6 4.4 4.3 7.2 6.1 1.1 1.7 8.5 7.6 ns t plh t phl oebn to bn waveform 1, 2 1.2 1.9 2.9 3.3 4.8 4.7 1.0 1.2 5.8 6.4 ns t tlh t thl output transition time, bn port (1.3v to 1.8v) test circuit and waveforms 1.2 0.4 3.0 1.5 ns t sk (o) output to output skew for multiple channels 1 waveform 3 0.4 1.0 2.0 ns t sk (p) pulse skew 2 ? t phl t plh ? max waveform 2 0.3 1.0 1.5 ns notes: 1. ? t pn actual t pm actual ? for any data input to output path compared to any other data input to output path where n and m are either lh or hl. skew times are valid only under same test conditions (temperature, v cc , loading, etc.). t sk (0) compares t plh on a given path to t plh on any other path or compares t phl on a given path to t phl on any other path. 2. t sk (p) is used to quantify duty cycle characteristics. in essence it compares the input signal duty cycle to the corresponding out put signal duty cycle (50mhz input frequency and 50% duty cycle, tested on data paths only).
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 11 ac electrical characteristics a to b 16.5 w load specifications symbol parameter test condition t amb = +25 c, v cc = 3.3v, t amb = 40 to +85 c, v cc = 3.3v 10%, unit min typ max min max t plh t phl propagation delay (thru latch) an to bn waveform 1, 2 1.4 1.2 2.7 2.4 3.9 3.6 1.0 1.0 5.0 4.0 ns t plh t phl propagation delay (transparent latch) an to bn waveform 1, 2 1.8 2.0 3.0 3.2 4.2 4.7 1.0 1.4 5.6 5.5 ns t plh t phl propagation delay lcab to bn (latch) waveform 1, 2 8.6 8.0 11.4 10.6 14.2 13.3 6.5 6.4 17.5 16.1 ns t plh t phl propagation delay lcab to bn (register) waveform 1, 2 2.2 2.3 3.5 3.7 4.8 5.1 1.2 1.7 6.1 5.9 ns t plh t phl propagation delay sel0 or sel1 to bn (inverting) waveform 1, 2 2.6 1.4 4.5 4.4 6.7 7.7 1.5 1.1 8.1 8.4 ns t plh t phl propagation delay sel0 or sel1 to bn (non-inverting) waveform 1, 2 2.2 2.3 4.5 4.0 6.9 5.8 1.4 1.5 8.2 6.9 ns t plh t phl oeb0 to bn waveform 1, 2 1.8 1.7 3.1 2.9 4.4 4.2 1.0 1.0 5.8 6.0 ns t tlh t thl output transition time, bn port (1.3v to 1.8v) test circuit and waveforms 1.2 0.4 3.0 1.5 ns t sk (o) output to output skew for multiple channels 1 waveform 3 0.5 1.0 2.0 ns t sk (p) pulse skew 2 ? t phl t plh ? max waveform 2 0.5 1.0 1.5 ns notes: 1. ? t pn actual t pm actual ? for any data input to output path compared to any other data input to output path where n and m are either lh or hl. skew times are valid only under same test conditions (temperature, v cc , loading, etc.). t sk (0) compares t plh on a given path to t plh on any other path or compares t phl on a given path to t phl on any other path. 2. t sk (p) is used to quantify duty cycle characteristics. in essence it compares the input signal duty cycle to the corresponding out put signal duty cycle (50mhz input frequency and 50% duty cycle, tested on data paths only).
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 12 ac setup requirements (commercial) limits symbol parameter test t amb = +25 c, v cc = 3.3v, t amb = 40 to +85 c, v cc = 3.3v 10%, unit symbol parameter condition c l = 50pf (a side) / c d = 30pf (b side) r l = 500 w (a side) / r u = 16.5 w (b side) unit min typ min t s (h) t s (l) setup time an to lcab waveform 4 1.3 1.3 1.5 1.5 ns t h (h) t h (l) hold time an to lcab waveform 4 1.0 1.0 1.0 1.0 ns t s (h) t s (l) setup time bn to lcba waveform 4 5.0 4.0 6.0 4.5 ns t h (h) t h (l) hold time bn to lcba waveform 4 0.0 0.0 0.0 0.0 ns t w (h) t w (l) pulse width, high or low lcab or lcba waveform 4 3.0 3.0 3.0 3.0 ns ac waveforms v m t s t pzl input output v m v m v m v m t plh t phl v m v m v m v m t phl t plh output an, bn an, bn v m v m t sk (o) an oea v m v m t plz v m v ol +0.3v an oea v m v m v m v oh -0.3v ov t phz t pzh note: v m = 1.55v for bn , v m = 1.5v for all others. input an, bn lcab, lcba v m v m 1/f max t h t s t h t w (l) t w (h) the shaded areas indicate when the input is permitted to change for predictable output performance. waveform 1. propagation delay for data or output enable to output waveform 2. propagation delay for data or output enable to output waveform 3. output to output skew waveform 4. setup and hold times, pulse widths and maximum frequency waveform 5. 3-state output enable time to high level and output disable time from high level waveform 6. 3-state output enable time to low level and output disable time from low level t w (input) t w (output) sg00062
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 13 test circuit and waveforms 2.5ns 2.0ns 500ns 500ns input pulse requirements rep. rate amplitude t tlh t thl 1mhz 3.0v 2.5ns input pulse definitions v m = 1.55v for bn , v m = 1.5v for all others. v cc family fb+ d.u.t. pulse generator 7.0v r l r l c l r t v in v out test circuit for 3-state outputs on a port test switch switch position t plz, t pzl all other closed open definitions: r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. c d = load capacitance includes jig and probe capacitance; see ac characteristics for value. r u = pull up resistor; see ac characteristics for value. t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse amp (v) low v low v t thl (t f ) t tlh (t r ) t w t w low v 0.0v t tlh (t r ) t thl (t f ) amp (v) a port 1mhz 2.0v 2.0ns 1.0v b port v cc d.u.t. pulse generator r u c d r t v in v out test circuit for outputs on b port bias v 2.0v (for r u = 9 w ) 2.1v (for r u = 16.5 w ) sg00063
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 14 qfp52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm sot379-1
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 15 notes
philips semiconductors product specification FBL2031 9-bit btl 3.3v latched/registered/pass-thru futurebus+ transceiver 2000 apr 18 16 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 04-00 document order number: 9397 750 07089

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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